When the SI is wider than the target MI, downsizing is performed and, in the transaction issued to the MI, the number of data beats is multiplied up accordingly.
- For writes, data serialization occurs on the W-channel between the SI and MI.
- For reads, data merging occurs on the R-channel between the MI and SI.
During merging, the read error response code (rresp) for each output data beat produced on the SI is set to the worst-case error condition encountered among the input data beats being merged, according to the following descending precedence order: DECERR, SLVERR, OKAY, EXOKAY.
On the AW or AR command channel, AXI Switch factors up the length of each burst and detects when the resulting burst length would exceed the maximum burst limit (256 data beats for AXI4, 16 for AXI3, or 1 for AXI4-Lite). In such cases, the core splits the transaction automatically into multiple conforming burst transactions.
When a downsized Write transaction results in splitting, the core coalesces the multiple Write responses received at the MI and issues one Write response on the SI. The core sets the error response code (BRESP) to the worst-case error condition encountered among the multiple input responses, according to the following descending precedence order: DECERR, SLVERR, OKAY.