There are two resets synchronous with two clocks used in the IP.
-
s_axi_cpu_resetn - Synchronous with
s_axi_cpu_clk. -
axis_resetn - Synchronous with
axis_clk.
Reset on AXI4-Stream will reset the AXI4-Lite registers as mentioned in the register space.
Reset on AXI4-Lite registers will need a whole system reset as well.
The resets have to asserted for a minimum of 16 clocks of the synchronous clock.