Port Descriptions - 1.0 English - PG451

Ethernet Offload Engine LogiCORE IP Product Guide (PG451)
Document ID
PG451
Release Date
2025-05-29
Version
1.0 English
Table 1. Interfaces
Signal Name Interface I/O Init Value Description
Clocks and Resets
axis_clk Clock I   Clock input for the module.
axis_resetn Reset I   Reset for axis_clk.
s_axi_cpu_clk Clock I   Clock input for AXI4-Lite register module (and timer module).
s_axi_cpu_resetn Reset I   Reset for s_axi_cpu_clk.
eoe_irq Interrupt O 0 Interrupt pin from EOE. For future use.
AXI4-Lite Interface
s_axi_cpu* AXI Lite Interface     For register programming.
RX AXIS Interface from MAC
rx_axis_* RX_AXIS Interface I/O   See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) for the AXI4 signal.

Data width can be configured as 32 or 64. Input from MAC carrying data received by MAC.
S2MM AXIS Interface to MCDMA
s2mm_axis_* S2MM_AXIS Interface I/O   See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) for the AXI4 signal.

Data width is 64. Data output to MCDMA with added TDEST value.
S2MM AXIS STATUS Interface to MCDMA
s2mm_axis_sts* S2MM_AXIS_STS Interface I/O   See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) for the AXI4 signal.

Data width is 32-bits. Carries the information about the data transmitted over s2mm_axis interface.
TX AXIS Interface to MAC
tx_axis_* TX_AXIS Interface I/O   See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) for the AXI4 signal.

Data width can be configures to 32- or 64-bits.

MM2S AXIS Interface from MCDMA
mm2s_axis_* MM2S_AXIS Interface I/O   See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) for the AXI4 signal.

Data width is 64-bits. Carries data input from MCDMA.
MM2S AXIS CONTROL Interface from MCDMA
mm2s_axis_ctrl* MM2S_AXIS_CTRL Interface I/O   See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) for the AXI4 signal.

Data width is 32-bits. Carries control information regarding the input stream from MCDMA.