Required Constraints
Clock frequency constraints are required for s_axi_cpu_clk and
axis_clk.
create_clock -name axis_clk -period 5 [get_ports axis_clk]
create_clock -name s_axi_cpu_clk -period 10 [get_ports s_axi_cpu_clk]The clock constraints are generated at system level; for example, using the clock wizard.
Device, Package, and Speed Grade Selections
Only supported on AMD UltraScale+™ families with GTHE4 or GTYE4 and AMD Versal™ adaptive SoCs with GTYE5 and GTYP.
Clock Frequencies
For details on the clocks used in the IP, refer to Clocking.
Clock Management
This section is not applicable for this IP core.
Clock Placement
This section is not applicable for this IP core.
Banking
This section is not applicable for this IP core.
Transceiver Placement
This section is not applicable for this IP core.
I/O Standard and Placement
This section is not applicable for this IP core.