Channel GRO Packet Counter Register (Channel Offset + 0x14) - 1.0 English

Channel GRO Packet Counter Register (Channel Offset + 0x14) - 1.0 English - PG451

Ethernet Offload Engine LogiCORE IP Product Guide (PG451)

Document ID

PG451

Release Date

2025-05-29

Version

1.0 English

Table 1. Channel GRO Packet Counter Register (Channel Offset + 0x14)
Bits	Name	Default Value	Access	Description
31:16	Reserved	0	-	Reserved
15:0	gro_packet_count_ch	0	RO	GRO Packet Count: Overflow counter for channel. Reset to AXI4-Stream resets this register to 0.
When axis_resetn is applied, only gro_en_ch in the Channel Control Register and the Error & Statistics Counter are reset to default values. All other registers are not affected. When s_axi_cpu_resetn is applied, all registers are set to zero.