Channel Control Register (Channel Offset + 0x0) - 1.0 English - PG451

Ethernet Offload Engine LogiCORE IP Product Guide (PG451)

Document ID
PG451
Release Date
2025-05-29
Version
1.0 English
Table 1. Channel Control Register (Channel Offset + 0x0)
Bits Name Default Value Access Description
31:24 protocol_ch1 8'd17 R/W Protocol of GRO for channel
23:1 Reserved 0 - Reserved
0 gro_en_ch 0 R/W GRO Enable for channel

Reset to AXI4-Stream resets this register to 0.