The LTPI IP uses the register address space as described in the LTPI Specification r 1.2, v 1.0RC3 , section 3.2 LTPI Control and Status Registers (CSR).
| Offset | Name | Description |
|---|---|---|
| 0x0000_0000 - 0x0000_01FF | CPLD/FPGA Information | The offset is reserved for OEM-defined CPLD/FPGA information such as CPLD/FPGA image version numbers, device identifiers, OEM specific information, and so on. |
| 0x0000_0200 - 0x0000_02FF | LTPI Control and Status | LTPI Status and Link Training Control Registers defined in the LTPI Specification r 1.2, v 1.0RC3 , section 3.2 LTPI Control and Status Registers (CSR). |
| 0x0000_0300 - 0x0000_03FF | Reserved | Reserved for future use |
| 0x0000_0400 - 0xFFFF_FFFF | Data Channel | Data Channel memory space. AXI4-Lite slaves need to have their address offset set accordingly to be accessed from SCM via data channel. |
The proprietary registers for this IP are shown in the following table:
| Offset (hex) | Register Name | Access | Default (hex) | Register | ||
|---|---|---|---|---|---|---|
| Bit Range | Field | Description | ||||
| 0x00 | LTPI and IP versions | RO | 0x01000300 | 31:24 | Major | LTPI Specification Version number |
| 23:16 | Minor | LTPI Specification Version number | ||||
| 15:8 | Major | LTPI IP Version | ||||
| 7:4 | Medium | LTPI IP Version | ||||
| 3:0 | Minor | LTPI IP Version | ||||
| 0x08 | Scratch register | RW | 0x0 | 31:0 | Scratch | Scratch register for testing data access |
| 0x10 | Interrupt status register | RC | 0x0 | 31:6 | Reserved | Reserved |
| 5 | ucs_err | Unknown comma symbol error interrupt | ||||
| 4 | ll_err | Link loss error interrupt | ||||
| 3 | crc_err | CRC error interrupt | ||||
| 2 | FRCNT_OOB | Out of bound error on received Frame Counter and no CRC error | ||||
| 1 | I2C_TO | I2C TO - see I2C TO registers for more details | ||||
| 0 | tr_conf | Trigger configuration State interrupt. Cleared by writing 1 to bit 11 of 0x280 | ||||
| 0x14 | Interrupt enable | RW | 0x1 | 31:6 | Reserved | Reserved |
| 5 | en_ucs_err | Enable unknown comma symbol error interrupt | ||||
| 4 | en_ll_err | Enable link loss error interrupt | ||||
| 3 | en_crc_err | Enable CRC error interrupt | ||||
| 2 | en_FRCNT_OOB | Enable FRCNT_OOB interrupt | ||||
| 1 | en_I2C_TO | Enable I2C_TO interrupt | ||||
| 0 | Reserved | Reserved | ||||
| 0x80 | I2C TO IF0 | RC | 0x0 | 31 | TO_IND | Timeout indicator = 1 if timeout happened |
| 30 | Cntr/Trgt | Controller/Target | ||||
| 29:12 | Reserved | Reserved | ||||
| 11 | scl_tri | Values of signal at the point of timeout | ||||
| 10 | sda_tri | |||||
| 9 | scl_in | |||||
| 8 | sda_in | |||||
| 7:4 | EVT_IN | Event in state | ||||
| 3:0 | EVT_OUT | Event out state | ||||
| 0x84 | I2C TO IF1 | RC | 0x0 | 31:0 | I2C timeout information, same as for IF0 | |
| 0x88 | I2C TO IF2 | RC | 0x0 | 31:0 | I2C timeout information, same as for IF0 | |
| 0x8C | I2C TO IF3 | RC | 0x0 | 31:0 | I2C timeout information, same as for IF0 | |
| 0x90 | I2C TO IF4 | RC | 0x0 | 31:0 | I2C timeout information, same as for IF0 | |
| 0x94 | I2C TO IF5 | RC | 0x0 | 31:0 | I2C timeout information, same as for IF0 | |
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