The functional block diagram of the core is shown in the following figure.
Figure 1. LTPI Architecture
Sub-blocks description:
- CSR
- The Configuration and Status registers provide a way for the BMC or other device on the SCM or HPM to control the operation of the LTPI logic. Access to this block is always available in SCM mode but requires DEBUG_MODE active to be present on HPM mode.
- External Interface Controllers
- Responsible for capturing and reconstructing of physical interfaces on LTPI channels:
- GPIO
- UART
- I2C/SMBus
- OEM
- Data Channel
- Channel Controller
- Responsible for:
- Link State Machine Control (Link Training and Interface Configuration)
- Generation of outgoing LTPI Frames
- Parsing of incoming LTPI Frames
- CRC Checksum Generation and Verification
- LVDS Interface Controller
- Responsible for:
- Serialization and Deserialization of the data on the LVDS Link
- Comma Symbol Chasing and Locking
- 8B/10B Encoding and Decoding