The full block diagram and explanation of LTPI link initialization and operation is described in section 4 of the LTPI Specification r 1.2, v 1.0RC3 . The following block diagram is taken from that document, with relevant notes.
- Note 1
- The time it takes to align to the beginning of the frame depends on time needed to achieve the DC-balance and how efficiently the comma symbol can be found (depends on the SERDES design). This stage is the source of initial misalignment between the SCM LTPI and HPM LTPI by means of number of frames sent and received. The number of frames sent should not be included in the minimum Frame Detect frames transmitted (255).
- Note 2
- This stage is expected to be entered by SCM and HPM at different timings due to the initial misalignment in the first stage. This means that one side can complete this stage earlier and move to the Link Speed stage. If it happens, then the ‘slower’ part switches to the Link Speed even if the required number of TX and RX frames is not achieved.
- Note 3
- Both sides keep sending Link Speed. SCM is required to send a minimum of seven Link Speed Frames, while HPM is required to receive three Link Speed Frames.
- Note 4
- Because the LTPI clock is reconfigured to a higher speed, the LTPI needs to realign to the beginning of the frames again, similar to the Link Detect stage. Typically, the phase-locked loop (PLL) is going to be reconfigured and requires some time to lock. To compensate for that, 100 ms timeout is used on both sides.
Upon reset, the LTPI IP goes into Link Detect state and goes through the various states, as described in the preceding figure, to reach the Operational state. In the Operational state, the LTPI IP provides tunneling of GPIO, UART, SMBus/I2C, OEM and data channel signals according to standards described in the LTPI Specification r 1.2, v 1.0RC3 and Datacenter - Secure Control Module (DC-SCM) r 2.2, v 1.0RC2 .
The maximum LVDS rate is determined by the SPD_CAP parameter. The chosen LVDS rate can be lower than that, depending on the partner side capabilities. The operational LVDS rate that is chosen in the Link Speed state determines some of the maximum rates of the external interfaces, as described in the following sections.