The example design project generates a top-level SystemVerilog file named example_design_testbench.sv that instantiates both block designs, the synthesizable example design, and the partner simulation model connecting them together.
LTPI example design test bench connects the synthesizable example design to its partner simulation model. LTPI provides basic stimulus generators, FIFOs, and checker blocks for each of the channel interfaces on the two LTPI’s interfaces. During simulation, channel traffic is tunneled in both directions between the two LTPIs.
Running a behavioral simulation causes the example design test case to initiate traffic from each channel’s stimulus generator block into an LTPI. Traffic then gets tunneled over LVDS to its partner LTPI and out to the corresponding checker block for comparison with a copy of the generated traffic bypassing both LTPIs via a FIFO.