|
Core Specifics |
| Supported Device Family |
AMD Artix™ 7, AMD
Artix™
UltraScale+
™, AMD Kintex™ 7, AMD Kintex™
UltraScale+™
, AMD Spartan™ 7 and
AMD Spartan™
UltraScale+™
FPGAs |
| Supported User Interfaces |
AXI4-Lite Interface, GPIO,
UART, SMBus/I2C, OEM, Data Channel |
| Provided with Core
|
| Design Files |
Encrypted Verilog RTL |
| Example Design |
System Verilog |
| Test Bench |
System Verilog |
| Constraints File |
XDC |
| Simulation Model |
Verilog Source Code |
| Supported S/W Driver |
N/A |
| Tested Design Flows
1
|
| Design Entry |
Standalone |
| Simulation |
For supported simulators, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973). |
| Synthesis |
AMD Vivado™
Synthesis |
| Support |
| Release Notes and Known Issues |
Master Answer Record: N/A |
|
Support web page
|
- For the supported versions of third-party
tools, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
|