GPIO - 3.0 English - PG448

LTPI IP Product Guide (PG448)

Document ID
PG448
Release Date
2025-11-20
Version
3.0 English

16 low latency (LL) and up to 1008 normal latency (NL) GPIO digital signals can be tunneled between the SCM and HPM side.

In the absence of CRC errors, the performance of LL GPIO is:

  • Latency lower than five frame periods. The frame period is calculated as 160/DR, where DR is the LVDS data rate (that is, DR = 400 MHz for 200 MHZ DDR LVDS, hence the frame period is 400 ns).
  • The maximum toggling rate of any GPIO signal is half that of the frame rate, that is, DR/320.

The performance of NL GPIO is dependent on NL_GPIO parameter and in the absence of CRC errors and data channel frames:

  • Latency is lower than ceil(NL_GPIO / 16) + 5 frame periods. Frame period is calculated as 160/DR, where DR is the LVDS data rate (that is, DR = 400 MHz for 200 MHZ DDR LVDS, hence the frame period is 400 ns).
  • The maximum toggling rate of any GPIO signal is 1/(2 x ceil(NL_GPIO / 16)) of the frame rate, that is, DR / (320 x ceil(NL_GPIO / 16)).