External Signals Interface - 3.0 English - PG448

LTPI IP Product Guide (PG448)
Document ID
PG448
Release Date
2025-11-20
Version
3.0 English
Table 1. External Signals Interface
Port Name I/O Clock Description
sys_clk I   System clock, default 25 MHz.
rst_n I N/A Active-Low system reset.
ll_gpi[15:0] I core_clk Low latency General Purpose inputs.
ll_gpo[15:0] O core_clk Low latency General Purpose outputs.
nl_gpi[NL_GPIO-1:0] I core_clk Normal latency General Purpose inputs.
nl_gpo[NL_GPIO-1:0] O core_clk Normal latency General Purpose outputs.
smb_scl_in[5:0] I core_clk SMBus/I2C SCL input.
smb_sda_in[5:0] I core_clk SMBus/I2C SDA input.
smb_scl_oe[5:0] O core_clk SMBus/I2C SCL tristate output enable.
smb_sda_oe[5:0] O core_clk SMBus/I2C SDA tristate output enable.
uart_rxd[1:0] I core_clk UART RXD input.
uart_cts[1:0] I core_clk UART CTS input.
uart_txd[1:0] O core_clk UART TXD output.
uart_rts[1:0] O core_clk UART RTS output.
aligned O core_clk Signal goes high once the Link Operational state is reached and stays high until link loss.
intrpt O core_clk Interrupt signal is used only when IP_MODE = SCM and it is a level signal where all enabled interrupts are ORed. See interrupt status and enabled registers in Table 2.
diag_led[7:0] O core_clk Diagnostics LEDs.
i2c_timeout_err O core_clk SMBus/I2C timeout error indication.
oem_din[OEM_DW-1:0] I core_clk OEM data input. Exists only if OEM channel is enabled.
oem_load O core_clk Indication when OEM input data is loaded. Exists only if OEM channel is enabled.
oem_dout[OEM_DW-1:0] O core_clk OEM data output. Exists only if OEM channel is enabled.
oem_ready O core_clk Indication when OEM output data is available. Exists only if OEM channel is enabled.
core_clk_out O   Core clock which runs most of the logic and sampling of all the IO signals that are being tunnelled over the LTPI.