Data Channel - 3.0 English - PG448

LTPI IP Product Guide (PG448)
Document ID
PG448
Release Date
2025-11-20
Version
3.0 English

When Data Channel is enabled, you can access memory mapped registers located on the HPM through the AXI4-Lite slave port on the SCM. Memory mapped access requests are issued on the SCM AXI4-Lite port, packaged into an LTPI frame, transferred to the HPM via LTPI and reproduced into an AXI4-Lite memory mapped request on the AXI4-Lite master port on the HPM. Upon request on the AXI4-Lite master port on the HPM, the AXI4-Lite slave responds, the response is packaged into the LTPI frame, transferred via LTPI to the SCM, where it is reproduced on the AXI4-Lite slave port. Only one outstanding transaction is permitted, meaning that a request for a new transaction can be made only after the response for the previous one has been returned. See the following figure which describes the data path for a memory mapped data channel over LTPI.

Note: Access to CSR on HPM is optional and requires enabling DEBUG_MODE. When DEBUG_MODE is enabled, the HPM CSR is visible through the AXI4-Lite slave port. You can then accesses the HPM CSR like any other port. See the following figure.
Figure 1. Memory Mapped Access through Data Channel

LTPI frame as well as memory mapped request commands are described in the LTPI Specification r 1.2, v 1.0RC3 in tables 12 and 13.

Note: As per the specification, the CRC is calculated for entire payload fields after the comma symbol of the LTPI Frame. CRC error is described as a command in Table 12, and it is supposed to be sent as a response from the HPM in case it received the data frame with the CRC error. The default data frame type is defined by the frame subtype which is the part of the payload. That means that the frame subtypes cannot be distinguished in the case of CRC errors, hence the HPM cannot determine that the CRC error happened for the data frame and therefore cannot generate the CRC error command. The same principle applies in the opposite direction, that is, the SCM cannot generate CRC error commands for the data frame.

Data channel allows abstraction of the memory mapped registers which are located on a separate board (HPM) by packaging those requests into LTPI data frames. This means that each request takes the time necessary to:

  1. Place a request on the SCM
  2. Form a frame
  3. Send it to the HPM
  4. Form a request on the far side (HPM)
  5. Wait for the memory mapped register’s response
  6. Receive a response
  7. Form a return frame
  8. Send it to the SCM
  9. Extract it from the frame and generate a response

This process takes time and means that each request on SCM side takes more than 10 LTPI frame periods to get a response. In the case of a slow AXI4-Lite slave on the HPM side, it could take significantly longer and in the case of an AXI4-Lite slave that is unresponsive, a timeout is necessary in order avoid stalling the system. The timeout is set so that:

  • A lack of response data frame received on the SCM for 500 µs causes a timeout. When a timeout occurs on the SCM side, an error response (code 10) is returned via bresp or rresp pins.
  • A lack of response on HPM AXI4-Lite master for 400 µs causes a timeout and generates a pulse on axil_to output, which you can use to reset the AXI4-Lite slaves. In this case a response data frame with information that a timeout has occurred on the HPM is sent to the SCM.