AXI4-Lite Signal Interface - 3.0 English - PG448

LTPI IP Product Guide (PG448)
Document ID
PG448
Release Date
2025-11-20
Version
3.0 English
Table 1. AXI4-Lite Signal Interface
Port Name I/O Clock Description
s_axi_aclk 1 I   SCM AXI4-Lite clock, default 100 MHz.
s_axi_aresetn 1 I s_axi_aclk Active-Low AXI4-Lite reset.
s_axi_awaddr[31:0] 1 I s_axi_aclk AXI4-Lite write address. Width of this bus is 32 b when Data Channel is enabled compared to 14 b not enabled.
s_axi_awvalid 1 I s_axi_aclk AXI4-Lite write address valid.
s_axi_awready 1 O s_axi_aclk AXI4-Lite write address ready.
s_axi_wdata[31:0] 1 I s_axi_aclk AXI4-Lite write data.
s_axi_wvalid 1 I s_axi_aclk AXI4-Lite write valid.
s_axi_wready 1 O s_axi_aclk AXI4-Lite write ready.
s_axi_bresp[1:0] 1 O s_axi_aclk AXI4-Lite write response.
s_axi_bvalid 1 O s_axi_aclk AXI4-Lite write response valid.
s_axi_bready 1 I s_axi_aclk AXI4-Lite write response ready.
s_axi_araddr[31:0] 1 I s_axi_aclk AXI4-Lite read address. Width of this bus is 32 b when Data Channel is enabled compared to 14 b when not enabled.
s_axi_arvalid 1 I s_axi_aclk AXI4-Lite read address valid.
s_axi_arready 1 O s_axi_aclk AXI4-Lite read address ready.
s_axi_rdata[31:0] 1 O s_axi_aclk AXI4-Lite read data.
s_axi_rresp[1:0] 1 O s_axi_aclk AXI4-Lite read response.
s_axi_rvalid 1 O s_axi_aclk AXI4-Lite read valid.
s_axi_rready 1 I s_axi_aclk AXI4-Lite read ready.
m_axi_aclk 2 I   HPM AXI4-Lite clock, default 100 MHz.
m_axi_aresetn 2 I m_axi_aclk Active-Low AXI4-Lite reset.
m_axi_awaddr[31:0] 2 O m_axi_aclk AXI4-Lite write address.
m_axi_awvalid 2 O m_axi_aclk AXI4-Lite write address valid.
m_axi_awready 2 I m_axi_aclk AXI4-Lite write address ready.
m_axi_wdata[31:0] 2 O m_axi_aclk AXI4-Lite write data.
m_axi_wvalid 2 O m_axi_aclk AXI4-Lite write valid.
m_axi_wready 2 I m_axi_aclk AXI4-Lite write ready.
m_axi_bresp[1:0] 2 I m_axi_aclk AXI4-Lite write response.
m_axi_bvalid 2 I m_axi_aclk AXI4-Lite write response valid.
m_axi_bready 2 O m_axi_aclk AXI4-Lite write response ready.
m_axi_araddr[31:0] 2 O m_axi_aclk AXI4-Lite read address.
m_axi_arvalid 2 O m_axi_aclk AXI4-Lite read address valid.
m_axi_arready 2 I m_axi_aclk AXI4-Lite read address ready.
m_axi_rdata[31:0] 2 I m_axi_aclk AXI4-Lite read data.
m_axi_rresp[1:0] 2 I m_axi_aclk AXI4-Lite read response.
m_axi_rvalid 2 I m_axi_aclk AXI4-Lite read valid.
m_axi_rready 2 O m_axi_aclk AXI4-Lite read ready.
axil_to 2 O m_axi_aclk AXI4-Lite master timeout. This signal (pulse) can be used to reset AXI4-Lite slaves on HPM side.
  1. Port available when IP_MODE=SCM or DEBUG_MODE = 1.
  2. Port only available if Data Channel is enabled, and only on HPM.