Register Space - Register Space - 3.0 English - PG447

H.264/H.265/JPEG Video Codec Unit 2 (VCU2) Solutions LogiCORE IP Product Guide (PG447)
Document ID
PG447
Release Date
2026-03-06
Version
3.0 English

This section details registers available in the VCU2 IP. The following table specifies the name, address, and description of each firmware addressable register within the VCU2 IP.

Table 1. VCU2 Registers
Address Offset Register Name Description
0x00 Version control register  
0x04 Soft Reset control register  
  1. Access type and reset value for all the reserved bits in the registers is read-only with value 0.
  2. Register accesses should be word aligned and there is no support for a write strobe. WSTRB is not used internally.
  3. Only the lower 6-bits (5:0) of the read and write address of the AXI4-Lite interface are decoded. This means that accessing address 0x00 and 0x40 results in reading the same address of 0x00.
  4. Reads and writes to addresses outside this table do not return an error.

The version control register is described in Table 2 and allows you to know the VCU2 IP version.

Table 2. Version Control Register (0x00)
Bits Name Reset Value Access Description
11-0 Version 'h300 Read only Details IP version
31-12 Reserved N/A N/A Reserved

The soft reset control register is described in Table 3, it allows you to reset Encoder and Decoder Instances of VCU2 IP.

Table 3. Soft Reset Control Register (0x04)
Bits Name Reset Value Access Description
31-2 Reserved N/A N/A Reserved
2 Raw Reset 1'b1 Read-Write

0: c0_raw_rst_n is under soft reset

1: c0_raw_rst_n is out of soft reset

  • After 8 clock cycles (s_axi_lite_clk), VCU2 instance comes out of soft reset, and this bit becomes 1'b1
  • To bring VCU2 instance out of soft reset before 8 clock cycles, write 1'b1 to this bit.
1 Decoder soft reset 1'b1 Read-Write

0: c0_pl_dec_rst_n is under soft reset

1: c0_pl_dec_rst_n is out of soft reset

  • After 8 clock cycles (s_axi_lite_clk), Decoder can come out of soft reset and this bit becomes 1'b1
  • To bring Decoder out of soft reset before 8 clock cycles, write 1'b1 to this bit.
0 Encoder soft reset 1'b1 Read-Write

0: c0_pl_enc_rst_n is under soft reset

1: c0_pl_enc_rst_n is out of soft reset

  • After 8 clock cycles (s_axi_lite_clk), Encoder can come out of soft reset and this bit becomes 1'b1
  • To bring Encoder out of soft reset before 8 clock cycles, write 1'b1 to this bit.