Port Descriptions - Port Descriptions - 3.0 English - PG447

H.264/H.265/JPEG Video Codec Unit 2 (VCU2) Solutions LogiCORE IP Product Guide (PG447)
Document ID
PG447
Release Date
2026-03-06
Version
3.0 English

The VCU2 core top-level signaling interface is shown in the following figure.

Figure 1. Core Ports
The following table summarizes the core interfaces.
Table 1. VCU2 Interfaces
Interface Name Interface Type Description
C0_ENC_M_AXI_NOC Memory mapped AXI4 master interface 128-bit memory mapped interface for Encoder block
C0_DEC_M_AXI_NOC Memory mapped AXI4 master interface 128-bit memory mapped interface for Decoder block
C0_ENC_MCU_M_AXI_NOC Memory mapped AXI4 master interface 128-bit memory mapped interface for Encoder MCU
C0_DEC_MCU_M_AXI_NOC Memory mapped AXI4 master interface 128-bit memory mapped interface for Decoder MCU
C0_S_AXI_NOC Memory mapped AXI4 slave interface 128-bit memory mapped interface for external master access
S_AXI__LITE Memory mapped AXI4-Lite slave interface AXI4-Lite memory map interface