The encoder core has two input signals: End of Line (EOL) and End of Frame (EOF), for the low latency feature. User modules should generate EOL/EOF signals.
The following figure describes how the Low latency Feature has been implemented in a design with the ISP Core as the input source to the encoder.
- Source Synchronization of Signals
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The encoder IP can receive source synchronization signals from a User Module indicating the availability of pixel data in the source picture memory buffer. There are the same number of source synchronization signals as the number of cores. With two cores available, two input sources can be synchronized. If source data is not available, as indicated by the synchronization signals, the encoder core will stall and not issue source data requests. The external source synchronization may be enabled/disabled using field Enc1SubFrameSrcSyncMode.
- The encoder interface includes the following signals:
- c0_vcu2_enc_sync_eol (end of 16 pixels lines) one clock cycle pulse
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c0_vcu2_enc_sync_eof (end of frame) at least one clock cycle pulse on the last EOL pulse of the frame
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