|
Core Specifics |
| Supported Device Family(1)
|
AMD Versal™ AI Edge Series Gen
2 and AMD Versal™ Prime Series Gen
2 devices |
| Supported User Interfaces |
AXI4-Lite, AXI4 MM |
| Resources |
N/A |
| Provided with
Core
|
| Design Files |
Unencrypted RTL |
| Example Design |
Provided |
| Constraints File |
Xilinx™ Design Constraints File (XDC) |
| Simulation Model |
Not Provided |
| Supported S/W Driver |
Linux kernel driver with firmware |
| Tested Design
Flows
2
|
| Design Entry |
AMD Vivado™ Design Suite
|
| Simulation |
Not Supported |
| Synthesis |
Vivado Synthesis |
| Support |
| All Vivado IP Change Logs |
Master AMD Vivado™
IP Change Logs: 72775
|
|
Support web page
|
- For a complete list of supported devices, see the AMD Vivado™
IP catalog.
- For the supported versions of the tools, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
|