Hardware-Low-Latency Mode - Hardware-Low-Latency Mode - 3.0 English - PG447

H.264/H.265/JPEG Video Codec Unit 2 (VCU2) Solutions LogiCORE IP Product Guide (PG447)

Document ID
PG447
Release Date
2026-03-06
Version
3.0 English

In hardware-low-latency mode, signals are supported that indicate how much an input or output frame has been filled. The encoder can suspend waiting for more data to become available. Also, a frame can be skipped when encoding is running behind.

The VCU2 encoder interprets an eol hardware signal that is signaled every 16 pixel-lines and an eof hardware signal marking the end of a frame. This, together with a frame index specifying the frame the encoder is working on, allows the encoder to suspend operation waiting for more data to become available. When using hardware low-latency mode there is a limit of one stream per encoder core (2 are available per VCU2 tile).

This requires the software to send a frame downstream before any data is captured or decoded.

A VCU2 decoder core outputs a 14-bit counter that indicates the progress in number of pixel-lines (in units of 4 pixel-lines). When using hardware low-latency mode there is a limit of one stream per decoder core (1 available).