The encoder engine is designed to process video streams using the HEVC (ISO/IEC 23008-2 High-Efficiency Video Coding) and AVC (ISO/IEC 14496-10 Advanced Video Coding) standards (no JPEG encoding is supported). It provides support for 8-bit, 10-bit and 12-bit color, Y only (monochrome), 4:2:0, 4:2:2 and 4:4:4 chroma formats and up to 4K UHD at 60 fps performance. Resolutions up to 8K are supported with reduced framerate at 15 fps. The encoder contains global registers, an interrupt controller, and a timer. The encoder is controlled by an integrated RISC-V 64-bit microcontroller unit (MCU). VCU2 applications running on the APU use the VCU2 Control Software library API to interact with the encoder MCU. The MCU firmware is not user modifiable.
The encoder features an integrated L2 cache with no requirement for use of PL BRAM or URAM, and supports tiled formats for reduced NoC and external memory interface bandwidth.