The decoder block is designed to decompresses video streams using the H.265 (HEVC) and H.264 (AVC) standards. It provides complete support for these standards, including support for 8-bit, 10-bit, and 12-bit color depth, 4:0:0, 4:2:0, 4:2:2 and 4:4:4 chroma formats, up to 4K UHD at 60 fps performance.
The IP hardware has direct access to the NOC through a high-bandwidth master interface to transfer video data to and from an external memory. The application runs on the APU while the VCU2 control software and firmware runs on a RISC-V MCU. The IP hardware is controlled by the embedded MCU using a register map to set decoding parameters through an internal peripheral bus.
The VCU2 decoder block is shown in the following figure.