The decoder engine can process video streams using the HEVC (ISO/IEC 23008-2 High Efficiency Video Coding), AVC (ISO/IEC 14496-10 Advanced Video Coding) and JPEG (ISO/IEC 10918-1 | ITU-T Recommendation T.81). It provides support for 8-bit, 10-bit, and 12-bit color depth, Y-only (monochrome), 4:2:0, 4:2:2 and 4:4:4 chroma formats, up to 4K UHD at 60 fps performance. It also contains global registers, an interrupt controller, and a timer.
The VCU2 decoder is controlled by a RISC-V 64-bit microcontroller unit (MCU). VCU2 applications running on the APU use the VCU2 Control Software library API to interact with the decoder MCU. The MCU firmware is not user modifiable.
The decoder includes control registers, a bridge unit, and a set of internal memories. The bridge unit manages the request arbitration, burst addresses, and burst lengths for all external memory accesses required by the decoder.