The following table summarizes the signals which are either shared by, or not part of the dedicated AXI4 interfaces.
| Port Name | Direction | Description |
|---|---|---|
| c0_pl_enc_rst_n | Input | Signal used to reset Encoder Interface |
| c0_pl_dec_rst_n | Input | Signal used to reset Decoder Interface |
| s_axi_lite_rst_n | Input | Signal used to generate vcu2_resetn_combined from LC_Register |
| c0_dpll_rst_n | Input | Signal used to reset DPLL blocks |
| dpll_ref_clk | Input |
DPLL reference clock input Note: Recommend to connect this pin to PS-PL
fabric clock. For Jitter requirement details, refer to Clocks and Reset section in
Versal Prime Series Gen 2 Data Sheet: DC and AC Switching
Characteristics (DS1020).
|
| s_axi_lite_aclk | Input | Clock input to S_AXI_LITE interface |
| c0_irq_error | Output | Combined Interrupt output from VCU2 |
| c0_irq_enc_pintreq | Output | Separate Encoder interrupt from VCU2 (Enabled when C0_ENABLE_ENCODER == True) |
| c0_irq_dec_pintreq | Output | Separate Decoder interrupt from VCU2 (Enabled when C0_ENABLE_DECODER == True) |
|
c0_enc_sync_eol_path0 c0_enc_sync_eol_path1 |
Input | End of Line signal - Low Latency mode encoder (Enabled when C0_ENC_ENABLE_LOW_LATENCY_MODE == True && C0_ENABLE_ENCODER == True) |
|
c0_enc_sync_eof_path0 c0_enc_sync_eof_path1 |
Input | End of Frame signal - Low Latency mode encoder (Enabled when C0_ENC_ENABLE_LOW_LATENCY_MODE == True && C0_ENABLE_ENCODER == True) |
| c0_dec_m_axi_noc_clk | Output | Output clock for C0_DEC_M_AXI Interface (Enabled when C0_ENABLE_DECODER == True) |
| c0_enc_m_axi_noc_clk | Output | Output clock for C0_ENC_M_AXI Interface (Enabled when C0_ENABLE_ENCODER == True) |
| c0_dec_mcu_m_axi_noc_clk | Output | Output clock for C0_DEC_MCU_M_AXI Interface (Enabled when C0_ENABLE_DECODER == True) |
| c0_enc_mcu_m_axi_noc_clk | Output | Output clock for C0_ENC_MCU_M_AXI Interface (Enabled when C0_ENABLE_ENCODER == True) |
| c0_raw_rst_n | Input | Signal used to reset VCU2 |
| c0_s_axi_noc_clk | Output | clk for nsu interface |
| c0_enc_mcu_m_axi_noc_clk | Output | clk for nsu interface |