Basic Configuration - Basic Configuration - 3.0 English - PG447

The following diagram displays the Basic Configuration tab on the GUI.

Enable Configuration

• Enable Encoder: Used to enable or disable encoder core.
  • TRUE: Encoder is enabled, set the encoder parameters.
  • FALSE: Encoder is disabled, which disables GUI options for encoder and corresponding encoder ports/interfaces.

• Enable Decoder: Used to enable or disable decoder core.
  • TRUE: Decoder is enabled, set the decoder parameters.
  • False: Decoder is disabled, which disables GUI options for decoder and corresponding decoder ports/interfaces.

Figure 1. Basic Configuration

Additional Configuration

Low Latency Mode - Hardware Synchronization: Low latency modes can be enabled by software configuration.

• True: Enables the following signals
  1. c0_enc_sync_eol_path0
  2. c0_enc_sync_eol_path1
  3. c0_enc_sync_eof_path0
  4. c0_enc_sync_eof_path1
  Figure 2. Low Latency Mode (Encoder) True
  
  
• False: Disables low latency support
  Figure 3. Low Latency Mode (Encoder) False

• Encoder Clock Configuration:
  • Core/MCU Clk:
    • Requested (MHz): Encoder Clock can be selected as per the following table based on speedgrade:

      Table 1. Encoder Clock Range

      Speedgrade	Range
      2LP	540 - 722
      1MP	540 - 912
      2MP	540 - 950
      2HP	540 - 1121
      default	540 - 950

    • Actual (MHz): This represents actual Encoder Clock generated from DPLL.
• Decoder Clock Configuration:
  • • Core/MCU Clk:
      • Requested (MHz): Decoder Clock can be selected as per following table based on speedgrade:

        Table 2. Decoder Clock Range

        Speedgrade	Range
        2LP	470 - 697.68
        1MP	470 - 881.28
        2MP	470 - 918
        2HP	470 - 1083.24
        default	470 - 918

      • Actual (MHz): This represents actual Decoder Clock generated from DPLL.