Structural Options Tab - Structural Options Tab - 1.0 English - PG442

Versal Adaptive SoC Transceiver Subsystem Product Guide (PG442)
Document ID
PG442
Release Date
2024-11-13
Version
1.0 English
Figure 1. Structural Options Tab
Include Clock Buffer instance in

IP customization options to include the clocking buffer in the IP core or example design. Based on the transceiver settings, this customization option can be restricted to only Example Design. The following are the configurations where the clocking buffer instance must be in the example design:

  1. Receiver Elastic Buffer Bypass Mode is set to Single Lane Mode for any of the interfaces.
  2. If the OUTCLK frequency is modified by the user from the default value as shown in the following figure. It is because the value of BUFG_GT dividers in the outclk to usrclk path of the transceiver needs to be adjusted accordingly.
    Figure 2. Transceiver Configuration Example
  3. The Master clock source selection in the Quad Interface Mapping Tab is customized as None.
Options to Enable Individual Ports
This tab provides customization options for enabling Quad-level ports according to your design preferences. Based on the configuration outlined in the wrapper configuration and quad interface mapping tab, mandatory ports are automatically enabled in the Structural Options tab. Customization options that are incompatible with the provided configuration are disabled. Optional ports are displayed in the GUI for you to enable based on your design requirements.