Structural Options Tab - Structural Options Tab - 1.0 English - PG442

Versal Adaptive SoC Transceiver Subsystem Product Guide (PG442)
Document_ID
PG442
Release_Date
2026-07-30
Version
1.0 English
Figure 1. Structural Options Tab
Include Clock Buffer instance in
Include the clocking buffer in the IP core or example design. Based on the transceiver settings, you can restrict this customization option to only the example design. The following configurations require that the clocking buffer instance is in the example design:
  1. Receiver Elastic Buffer Bypass Mode is set to Single Lane Mode for any of the interfaces.
  2. As shown in the following figure, the OUTCLK frequency is set to a value different from the default. It is because the value of BUFG_GT dividers in the outclk to usrclk path of the transceiver need to be adjusted accordingly.
    Figure 2. Transceiver Configuration Example
  3. The Master clock source selection in the Quad Interface Mapping Tab is customized as None.
Options to Enable Individual Ports
Provides customization options for enabling quad-level ports according to your design preferences. Based on the configuration outlined in the wrapper configuration and quad interface mapping tab, mandatory ports automatically enable in the Structural Options tab. Customization options incompatible with the provided configuration are disabled. Optional ports display in the GUI for you to enable based on your design requirements.