Simulation Waveform Showing Rate Change - Simulation Waveform Showing Rate Change - 1.0 English - PG442

Drive the rate port with 0 until the initial INTF*_rst_tx/rx_done_out asserts. The default value of INTF*_rst_tx/rx_done_out is high until gtpowergood is asserted high and goes low when ch*_tx/rxmstreset is applied to the quad. Finally, it measures the expected user clock frequency to ensure the expected line rate is achieved.

After every rate change, the following message prints:

  INTF0 RATE CHANGE INITIATED
INTF0 CONFIG1 ::::: TX RESET DONE asserted
INTF0 CONFIG1 ::::::: TXUSRCLK Frequency = 375.059
INTF0 CONFIG1 ::::::: TX_USER_CLOCK IS PROPER. TX_USER_CLOCK is 375.059 and EXPECTED is [371.25:378.75]
INTF0 CONFIG1 ::::: RX RESET DONE asserted
INTF0 CONFIG1 ::::::: RXUSRCLK Frequency = 375.059
INTF0 CONFIG1 ::::::: RX_USER_CLOCK IS PROPER. RX_USER_CLOCK POST PLL LOCK is 375.059 and EXPECTED is [371.25:378.75]
INTF0 POST CONFIG1 LINK STABLE TXUSRCLK Frequency = 375.059
INTF0 CONFIG1 ::::: POST LINK STABLE RXUSRCLK Frequency = 375.059

Finally, the following messages print to the transcript, indicating the test is passed:

  INTF0 RATE CHANGE INITIATED
INTF0 CONFIG3 ::::: TX RESET DONE asserted
INTF0 CONFIG3 ::::::: TXUSRCLK Frequency = 250.039
INTF0 CONFIG3 ::::::: TX_USER_CLOCK IS PROPER. TX_USER_CLOCK is 250.039 and EXPECTED is [247.5:252.5]
INTF0 CONFIG3 ::::: RX RESET DONE asserted
INTF0 CONFIG3 ::::::: RXUSRCLK Frequency = 250.039
INTF0 CONFIG3 ::::::: RX_USER_CLOCK IS PROPER. RX_USER_CLOCK POST PLL LOCK is 250.039 and EXPECTED is [247.5:252.5]
INTF0 POST CONFIG3 LINK STABLE TXUSRCLK Frequency = 250.039
INTF0 CONFIG3 ::::: POST LINK STABLE RXUSRCLK Frequency = 250.039
Time :        290518 ns   PASS: simulation completed
**   Test completed successfully