Reset Sequencing and Other Services - Reset Sequencing and Other Services - 1.0 English - PG442

The transmitter and receiver reset state machines implement the relevant master reset sequences as specified in the AMD Versal™ Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002) or Versal Adaptive SoC GTM Transceivers Architecture Manual (AM017). The reset controller helper block transceiver interface connects to the transceiver primitives. Following device configuration, no reset helper block reset inputs should be asserted until transceiver power is reported as good. The reset controller helper block internally holds all PLL and datapath resources in reset until GTPOWERGOOD is High from the GT Quad and then resets all transceiver resources by transitioning once through the transmitter and receiver state machines. As a result, you should wait for either the initial assertion of the gtpowergood port on the GT Wizard subsystem, or of both INTF*_rst_tx_done_out and INTF*_rst_rx_done_out before attempting subsequent resets of any kind.