The transmitter and receiver reset state machines implement the relevant master reset sequences specified in the Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002) or Versal Adaptive SoC GTM Transceivers Architecture Manual (AM017). The reset controller helper block transceiver interface connects to the transceiver primitives.
After device configuration, do no assert any reset helper block reset
inputs until the system reports that transceiver power is good. The reset controller
helper block internally holds all PLL and datapath resources in reset until the GT Quad
asserts GTPOWERGOOD High. It then resets all
transceiver resources by transitioning one time through the transmitter and receiver
state machines.
As a result, wait for either the initial assertion of the gtpowergood port on the GT Wizard subsystem or the
assertion of both INTF*_rst_tx_done_out and INTF*_rst_rx_done_out before attempting any subsequent
resets.
refclk is stable), when INTF*_rst_tx_done_out and INTF*_rst_rx_done_out assert, the reset can take up to 150 ms to complete.
The time taken varies depending on the GT configuration. This behavior holds true for
the following configurations:- Production rev silicon
- Full GT reset (TX/RX)
- All four channels/QUAD when used with the default configuration
-
NPICLK= 300 MHz