Reset Controller Helper Block - Reset Controller Helper Block - 1.0 English

Provide the Reset Controller helper block with the free running clock gtwiz_reset_clk_freerun_in that you specify during IP customization. A wizard subsystem delivers a single instance of the helper block for each interface added.

Table 1. Reset Controller Helper Block Ports
Name	Direction	Width	Clock Domain	Description
gtwiz_reset_clk_freerun_in	I	1	ASYNC	Free running clock to reset transceiver primitives (recommended between 100 MHz and 300 MHz and less than the internal frequency of the lowest line rate used). It needs to be toggling and stable before the GT Wizard sequence is initiated. Can be sourced from the PL output clock from CIPS.
gtwiz_reset_all_in	I	1	ASYNC	Signal to reset the phase-locked loops (PLLs) and active data directions of transceiver primitives. The falling edge of an active-High, asynchronous pulse of at least one gtwiz_reset_clk_freerun_in period in the duration initializes the process.
gtwiz_reset_tx_pll_and_datapath_in	I	1	ASYNC	Signal to reset the transmit data direction and associated PLLs of transceiver primitives. An active-High, asynchronous pulse of at least one gtwiz_reset_clk_freerun_in period in the duration initializes the process.
gtwiz_reset_tx_datapath_in	I	1	ASYNC	Signal to reset the transmit data direction of transceiver primitives. An active-High, asynchronous pulse of at least one gtwiz_reset_clk_freerun_in period in the duration initializes the process.
gtwiz_reset_rx_pll_and_datapath_in	I	1	ASYNC	Signal to reset the receive data direction and associated PLLs of transceiver primitives. An active-High, asynchronous pulse of at least one gtwiz_reset_clk_freerun_in period in the duration initializes the process.
gtwiz_reset_rx_datapath_in	I	1	ASYNC	Signal to reset the receive data direction of transceiver primitives. An active-High, asynchronous pulse of at least one gtwiz_reset_clk_freerun_in period in the duration initializes the process.
gtpowergood_in	I	1	ASYNC	Connects to GTPOWERGOOD signals produced by the transceiver channel logic.
gtwiz_reset_userclk_tx_active_in	I	1	ASYNC	For GTY, GTYP: Logical AND of all TXPMARESETDONE signals produced by the transceiver channel primitives. For GTM: Logical AND of all TXPROGDIVRESETDONE signals produced by the transceiver channel primitives
gtwiz_reset_userclk_rx_active_in	I	1	ASYNC	For GTY, GTYP: Logical AND of all RXPMARESETDONE signals produced by the transceiver channel primitives. For GTY, GTYP: Logical AND of all RXPMARESETDONE signals produced by the transceiver channel primitives.
mst_tx_resetdone	I	1	ASYNC	Logical AND of all MSTTXRESETDONE signals produced by transceiver channel primitives.
mst_rx_resetdone	I	1	ASYNC	Logical AND of all MSTRXRESETDONE signals produced by the transceiver channel primitives.
mst_tx_reset	O	1	gtwiz_reset_clk_freerun_in	Active-High signal fanned out to TXMSTRESET port of transceiver channels.
mst_rx_reset	O	1	gtwiz_reset_clk_freerun_in	Active-High signal fanned out to RXMSTRESET port of transceiver channels.
mst_tx_dp_reset	O	1	gtwiz_reset_clk_freerun_in	Active-High signal fanned out to TXMSTDATAPATHRESET port of transceiver channels.
mst_rx_dp_reset	O	1	gtwiz_reset_clk_freerun_in	Active-High signal fanned out to RXMSTDATAPATHRESET port of transceiver channels.
txuserrdy_out	O	1	gtwiz_reset_clk_freerun_in	Active-High signal fanned out to TXUSERRDY port of all transceiver channel primitives.
rxuserrdy_out	O	1	gtwiz_reset_clk_freerun_in	Active-High signal fanned out to RXUSERRDY port of all transceiver channel primitives.
gtwiz_reset_tx_done_out	O	1	gtwiz_reset_clk_freerun_in	Active-High indication that the transmitter reset sequence of transceiver primitives, as initiated by the reset controller helper block, is completed.
gtwiz_reset_rx_done_out	O	1	gtwiz_reset_clk_freerun_in	Active-High indication that the receiver reset sequence of transceiver primitives, as initiated by the reset controller helper block, is completed.
tx_clr_out	O	1	gtwiz_reset_clk_freerun_in	Active-High signal fanned out to clr_out port of clocking buffer module in transmitter clock path.
rx_clr_out	O	1	gtwiz_reset_clk_freerun_in	Active-High signal fanned out to clr_out port of clocking buffer module in receiver clock path.
tx_clrb_leaf_out	O	1	gtwiz_reset_clk_freerun_in	Active-Low signal fanned out to clrb_leaf port of clocking buffer module in transmitter path.
rx_clrb_leaf_out	O	1	gtwiz_reset_clk_freerun_in	Active-Low signal fanned out to clrb_leaf port of clocking buffer module in receiver path.

The helper block follows the controller reset sequence and contains the following two state machines:

Transmitter Reset State Machine: Resets the transmitter PLL and/or the transmitter datapath of all transceiver primitives and indicates their completion.
Figure 1. Transmitter Reset State Machine
Receiver Reset State Machine: Resets the receiver PLL and/or the receiver datapath of all transceiver primitives and indicates their completion.
Figure 2. Receiver Reset State Machine

The gtwiz_reset_all_in input initiates both transmitter and receiver state machines. The transmitter and receiver reset state machines are independent of one another. Each initiate either directly through the user interface if needed or the gtwiz_reset_all_in input controls them.

When the gtwiz_reset_all_in signal is activated, the transmitter and receiver state machines initiate simultaneously. If the channel configuration is set up so the receiver incoming data is dependent on the transmitter data, the receiver needs to go through a separate datapath reset after the gtwiz_reset_all_in completes, or use the reset_tx_pll_and_datapath followed by reset_rx_datapath.

The subsystem boundary includes the following reset ports that connect to the reset FSM module.

Note: Although the TX and RX reset FSMs operate independently, asserting individual resets must be carefully considered in transceiver configurations where shared resources impact both data paths. A common example is a shared PLL (that is, RPLL/LCPLL) used by both TX and RX — asserting a PLL reset, or any reset that propagates to the shared PLL, also disrupts the opposite data path. In such configurations, plan reset sequencing to account for the combined TX/RX impact.

Table 2. Reset Ports on the Subsystem Boundary
Name	Direction	Description
INTF*_rst_all_in	I	Connects to the gtwiz_reset_all_in port of the reset controller module.
INTF*_rst_tx_pll_and_datapath_in	I	Connects to the gtwiz_reset_tx_pll_and_datapath_in port of the reset controller module.
INTF*_rst_rx_pll_and_datapath_in	I	Connects to the gtwiz_reset_rx_pll_and_datapath_in port of the reset controller module.
INTF*_rst_tx_datapath_in	I	Connects to the gtwiz_reset_tx_datapath_in port of the reset controller module.
INTF*_rst_rx_datapath_in	I	Connects to the gtwiz_reset_rx_datapath_in port of the reset controller module.
INTF*_rst_tx_done_out	O	Connects to the gtwiz_reset_tx_done_out port of the reset controller module.
INTF*_rst_rx_done_out	O	Connects to the gtwiz_reset_rx_done_out port of the reset controller module.
INTF*_TX_clr_out	O	Connects to tx_clr_out port of the Reset controller module.
INTF*_RX_clr_out	O	Connects to the rx_clr_out port of the reset controller module.
INTF*_TX_clrb_leaf_out	O	Connects to the tx_clrb_leaf_out port of the reset controller module.
INTF*_RX_clrb_leaf_out	O	Connects to the rx_clrb_leaf_out port of the reset controller module.

Reset Controller Helper Block - Reset Controller Helper Block - 1.0 English - PG442

Versal Adaptive SoC Transceiver Subsystem Product Guide (PG442)