Product Specification - Product Specification - 1.0 English - PG442

The AMD Versal Adaptive SoC Transceiver Subsystem is a wrapper created around GT*_QUAD primitives. The wizard offers a highly-adaptable AMD Vivado™ IDE-driven customization process. It allows for basic customization of transceiver modes, optional port enablement interface, and instantiation of clocking helper blocks. It initializes, configures, and links a GT*_QUAD primitive and includes simulation support to demonstrate various GT Quad features. The Wizard subsystem enables the sharing of multiple Interface IPs, with each supporting multiple line rates.

Versal Adaptive SoC Transceiver Subsystem supports the following:

• A single wizard subsystem core instantiates a maximum of five GT*_QUAD primitive.
• A single wizard subsystem core shares a maximum of eight Interface IPs.
• Simplex and Duplex configurations support:
  1. Preset configurations for common standards.
  2. Full control of parameters for fine-tuning.
• Native support for dynamic line rate changing, eliminating the requirement for reprogramming or building an APB3 controller. You can configure up to 16 line rates per channel in each direction.

The subsystem is based on the older version of the transceiver GT QUAD IP (gt_quad_base) that instantiates the GT*_QUAD primitive. As shown in the following section, the subsystem is a wrapper around GT QUAD IPs, Reset FSM, and clocking helper blocks for various configurations.

Figure 1. Single Interface Single Quad

Figure 2. Multiple Interfaces Single Quad

Figure 3. Single Interface Multi Quad

Figure 4. Multi Interface Multi Quad

For IP port list and definitions, refer to the Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002) and Versal Adaptive SoC GTM Transceivers Architecture Manual (AM017).