Product Specification - Product Specification - 1.0 English - PG442

AMD Versal Adaptive SoC Transceiver Subsystem is a wrapper created around GT*_QUAD primitives. The wizard offers a highly adaptable AMD Vivado™ IDE-driven customization process. It allows for basic customization of transceiver modes, optional port enablement interface, and instantiation of clocking helper blocks. It initializes, configures, and links a GT*_QUAD primitive and includes simulation support to demonstrate various GT Quad features. The Wizard subsystem enables the sharing of multiple Interface IPs, with each supporting multiple line rates.

Versal Adaptive SoC Transceiver Subsystem supports the following:

• A single wizard subsystem core can instantiate a maximum of five GT*_QUAD primitive.
• A single wizard subsystem core can share a maximum of eight Interface IPs.
• Simplex and Duplex configurations support:
  1. Preset configurations for common standards.
  2. Full control of parameters for fine-tuning.
• Native support for dynamic line rate changing, eliminating the requirement for reprogramming or building an APB3 controller. Up to 16 line rates can be configured per channel in each direction.

Wizard subsystem is created based on the older version of transceiver GT QUAD IP (gt_quad_base) that instantiates GT*_QUAD primitive. As illustrated in the following section, the Wizard subsystem is a wrapper around GT QUAD IPs, Reset FSM, and clocking helper blocks for various configurations.

Figure 1. Single Interface Single Quad

Figure 2. Multiple Interfaces Single Quad

Figure 3. Single Interface Multi Quad

Figure 4. Multi Interface Multi Quad

For port list and definitions of this IP, see Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002) and Versal Adaptive SoC GTM Transceivers Architecture Manual (AM017).