The example design is the recommended means of simulating or implementing an instance of the Wizard IP core outside the context of your own system. It is quite simple to use, and you need to understand the following limitations:
- The example design does not implement specific protocols to generate or check data. Fundamentally, raw PRBS data is generated and checked.
- When the example design is simulated using the provided test bench, each transceiver channel is looped back from the serial data transmitter to the receiver. Data integrity can only be properly checked if the transmitter and receiver are configured for the same line rate and to use the same data coding. No rate adjustment schemes are used. If the transmitter and receiver line rates or data coding are configured differently in your system, cross-couple two appropriately customized core instances and check for data integrity in hardware or in your own test bench. In such a setup, the transmitter of core instance A is rate and coding matched to the receiver of core instance B, and vice-versa.
- The example design generation is limited for certain configurations. When user
tries to generate the example design for those configurations, an error dialog box
is displayed with the relevant message as shown
below:
Example design is not supported: Example design is not supported as requested number of reference clocks are not routable in example design. To override this, please set the parameter EN_EXDES_REFCLK_CHECK_BYPASS to true on the IP instance and then open the example design. User need to take care of the Reference clock placement.
The following are the scenarios where example design generation is restricted:
- For PCIe-related configurations
- For GTM Simplex configuration
- When the selected part doesn't have transceivers that can be accessed by PL logic
- If the requested reference clock sources exceed the number of reference clock sources available for the selected part
- If the clock buffers are instantiated in the example design and the respective master clock source ports are not enabled in the core