Limitations of the Example Design - Limitations of the Example Design - 1.0 English - PG442

Use the example design for simulating or implementing an instance of the Wizard IP core outside the context of your own system. It is quite simple to use, and you need to understand the following limitations:

• The example design does not implement specific protocols to generate or check data. Fundamentally, raw PRBS data is generated and checked.
• The example design does not exercise APB transactions. Attempting to simulate an APB transaction through the example design can result in simulation failures.
  Note: To simulate APB3 transactions in the example design test bench, initialize APB3PRESETN by asserting it low (0) at the start of the simulation, then deasserting it (driving it high) before accessing the APB3 interface. If APB3PRESETN is not properly initialized and released, accesses to some APB3 addresses cause the APB3 interface to hang in simulation.
• When the example design simulates using the provided test bench. Each transceiver channel loops back from the serial data transmitter to the receiver. Data integrity can only be properly checked if the transmitter and receiver are configured for the same line rate and to use the same data coding. No rate adjustment schemes are used. If the transmitter and receiver line rates or data coding are configured differently in your system, cross-couple two appropriately customized core instances and check for data integrity in hardware or in your own test bench. In such a setup, the transmitter of core instance A is rate and coding matched to the receiver of core instance B, and vice-versa.
• The example design generation is limited for certain configurations. When you try to generate the example design for those configurations, an error dialog box displays with following relevant message:

  Example design is not supported:
  Example design is not supported as requested number of reference clocks are not routable in example design. To override this, please set the parameter EN_EXDES_REFCLK_CHECK_BYPASS to true on the IP instance and then open the example design. User need to take care of the Reference clock placement.

The following scenarios restrict example design generation:

• PCIe-related configurations
• GTM Simplex configuration
• The selected part does not provide transceivers accessible to the PL logic
• The requested reference clock sources exceed the number of reference clock sources available for the selected part
• The example design instantiates clock buffers but does not enable the respective master clock source ports in the core