|
Subsystem Specifics |
| Supported Device Family |
AMD Versal™
Adaptive SoC |
| Supported User Interfaces |
N/A
|
| Resources |
N/A |
| Provided with Subsystem
|
| Design Files |
RTL |
| Example Design |
Verilog |
| Test Bench |
Verilog |
| Constraints File |
Xilinx Design Constraints (XDC) |
| Simulation Model |
Source HDL with SecureIP transceiver simulation
|
| Supported S/W Driver |
N/A |
| Tested Design Flows |
| Design Entry |
AMD Vivado™ Design Suite
|
| Simulation |
For supported simulators, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973). |
| Synthesis |
Vivado
Synthesis |
| Support |
| Release Notes and Known Issues |
Master Answer Record: 75716
|
| All Vivado IP Change
Logs |
Master Vivado IP Change Logs: 72775
|
|
Support web
page
|
- For a complete list of supported devices, see
the AMD Vivado™
IP catalog.
- For the supported versions of the tools, see
the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
|