This chapter provides information about the example design in the AMD Vivado™ Design Suite.
An example design can be generated for any instance of the Transceivers
Wizard IP core. After you customize and generate a core instance, select Open IP Example
Design option for that instance. A separate Vivado project
opens with the wizard example design as the top-level module. The example design instantiates
the customized core, add prbs_generator_checker_ip and does
the connections for the given configuration.
The following figure shows the hierarchy and simplified representation of the wizard subsytem of the example design top level module, which is used for simulation and implementation.
The purpose of the Wizard IP example design is to:
- Provide a simple demonstration of the customized core instance operating in simulation through the use of a link status indicator based on PRBS generators and checkers.
- Provide a starting point for integrating the customized core into your system, including reference clock buffers.
The prbs_generator_checker contains configurable PRBS generator and checker
modules per transceiver channel that enable simple data integrity testing and resulting link
status reporting. The example design is also synthesizable.
The example design uses sample GT Quad and GT REFCLK location for the device selected. The XDC needs to be updated based on the board layout if the expectation is to program the PDI.
The example design has additional top-level wrapper with the instantiation of VIOs to exercise the resets, rate change, and check the status of reset done and link status. The top-level VIO wrapper is suited when the example design is targeted for any board and the behavior of the wizard subsystem can be exercised using the VIOs.