This chapter provides information about the example design in the AMD Vivado™ Design Suite.
You can generate an example design for any instance of the Transceivers
Wizard IP core. After you customize and generate a core instance, select Open IP Example
Design option for that instance. A separate Vivado project
opens with the wizard example design as the top-level module. The example design instantiates
the customized core, adds prbs_generator_checker_ip, and does
the connections for the given configuration.
The following figure shows the hierarchy and simplified representation of the wizard subsystem of the example design top level module for simulation and implementation.
The Wizard IP example design:
- Provides a simple demonstration of the customized core instance operating in simulation through the use of a link status indicator based on PRBS generators and checkers.
- Provides a starting point for integrating the customized core into your system, including reference clock buffers.
The prbs_generator_checker contains a
configurable PRBS generator and checker modules per transceiver channel enabling simple data
integrity testing and the resulting link status reporting. The example design is also
synthesizable.
The example design uses sample GT Quad and GT REFCLK location for the device selected. The XDC needs to be updated based on the board layout if the expectation is to program the PDI.
The example design includes an additional top-level wrapper with the instantiation of VIOs to exercise the resets, rate change, and check the status of reset done and link status. Use the top-level VIO wrapper when the example design targets any board and the behavior of the wizard subsystem can be exercised using the VIOs.