Ultra-Low Power State - Ultra-Low Power State - 1.0 English - PG436

MIPI TX C-PHY/D-PHY LogiCORE IP Product Guide (PG436)

Document ID
PG436
Release Date
2025-11-20
Version
1.0 English

This is one type of escape mode and is supported by both the clock lane and data lane. You can exit the ultra-low power state by doing the following:

  • If the D-PHY RX ULPS WAKEUP counter for 1 ms time option is selected, D-PHY TX must send the Mark-1 (LP-10) state for a duration of 1 ms or longer, then drive the stop-state to make RX exits from the ULPS state.
  • If the D-PHY RX ULPS WAKEUP counter for 1 ms time option is not selected, then D-PHY RX IP checks only for the Mark-1 (LP-10) transition to exit from the ULPS mode.