The MIPI TX PHY delivers a demonstration test bench for the example design. The test bench consists of the following modules:
- Device Under Test (DUT)
- Clock and reset generator
- Status monitor
The example design demonstration test bench is a simple Verilog module to exercise the example design and the core itself. It simulates an instance of the MIPI TX PHY that is externally looped back to the MIPI RX PHY. The MIPI TX PHY Design test bench generates all the required clocks and resets.
- MIPI C-PHY/D-PHY Frame Generator
- Frame-Gen generates the packets of PRBS data type and streams to the TX-PHY through PPI.
- MIPI TX PHY
- TX-PHY receives the data from Frame-Gen through PPI and streams to RX-PHY through C-PHY/D-PHY interface.
- MIPI RX PHY
- RX-PHY receives the data through TX-RX loopback and streams to Frame_Checker through PPI.
- MIPI C-PHY/D-PHY Frame Checker
- Frame-Checker receives PPI data from RX PHY and checks the data and packet count registers to provide a pass/fail test result.