Shared Logic in Example Design - Shared Logic in Example Design - 1.0 English - PG436

Select Include Shared Logic in example design if:

• There should be at least one MIPI TX CPHY/DPHY IP with Include shared Logic in the Core mode whose outputs for shared resources can be used in other MIPI TX CPHY/DPHY IP generated with Include shared logic in example design mode.

• This is the second MIPI TX CPHY/DPHY core in a multi-core design.
• You only want to manage one customization of the MIPI RX CPHY/DPHY core in your design.
• You want direct access to the input clocks.

To fully use the MMCM and PLL, customize one MIPI TX CPHY/DPHY core with shared logic in the core and one with shared logic in the example design. You can connect the MMCM/PLL outputs from the first MIPI TX CPHY/DPHY core to the second core.

If you want fine control, you can select Include shared logic in example design and base your own logic on the shared logic produced in the example design.

Following things should also be taken into consideration while connecting Master & Slave cores:

1. Master and slave cores should have the same CLKOUTPHY clock frequency.
2. TX master and slave cores should be configured with the same line rate when sharing clock resources.
3. Additionally, MIPI TX CPHY/DPHY core can share master/slave clock resources, only if the TXCLKESC is configured with the same clock frequency for escape mode.