Shared Logic in Example Design - Shared Logic in Example Design - 1.0 English - PG436

Select Include Shared Logic in example design if:

• There needs to be at least one MIPI TX C-PHY/D-PHY IP with Include shared Logic in the Core mode whose outputs for shared resources can be used in other MIPI TX C-PHY/D-PHY IP generated with Include shared logic in example design mode.

• This is the second MIPI TX C-PHY/D-PHY core in a multi-core design.
• You only want to manage one customization of the MIPI TX C-PHY/D-PHY core in your design.
• You want direct access to the input clocks.

To fully use the MMCM and PLL, customize one MIPI TX C-PHY/D-PHY core with shared logic in the core and one with shared logic in the example design. You can connect the MMCM/PLL outputs from the first MIPI RX C-PHY/D-PHY core to the second core.

If you want fine control, you select Include shared logic in example design and base your own logic on the shared logic produced in the example design.

The following need to also be taken into consideration while connecting Master and Slave cores:

1. Master and slave cores need to have the same CLKOUTPHY clock frequency.
2. RX master and slave cores need to be configured with the same line rate when sharing clock resources.
3. Additionally, MIPI TX C-PHY/D-PHY core can share master/slave clock resources, only if the TXCLKESC is configured with the same clock frequency for escape mode.