The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 06/23/2026 Version 1.0 | |
| IP Facts | Added Performance and Resource Utilization link. |
| Features | Added four data lane C-PHY configuration support. |
| Overview | Updated figure. |
| Unsupported Features | Updated to include Calibration Format 3. |
| Performance and Resource Utilization | Added topic. |
| PPI Signals | Updated dl_txdatawidthhs and dl_txpreambletypehssignals descriptions. |
| CONTROL Register (0x0) | Updated phy_mode default value. |
| HS_TIMEOUT Register (0x10 offset) | Update C-PHY range. |
| PROGRAMMABLE SEQUENCE CONTROL Register (0x38) | Added note for programmable sequence insertion. |
| PROGRAMMABLE SEQUENCE DATA0 Register (0x3C) | Added note for programmable sequence insertion. |
| PROGRAMMABLE SEQUENCE DATA1 Register (0x40) | Added note for programmable sequence insertion. |
| User Parameters | Updated PHY mode default value. |
| Example Design | Added chapter. |
| 11/20/2025 Version 1.0 | |
| I/O Planning | Updated the section. |
| 05/29/2025 Version 1.0 | |
| PPI Signals | Updated the HS Signal table. |
| Clocking and Reset Signals | Updated the table. |
| HS_TIMEOUT Register (0x10 offset) | Updated the table. |
| 01/30/2025 Version 1.0 | |
| Initial release | N/A |