A high-speed clock is generated from the clock lane and is used for high-speed operations. The line status is detected based on low-power signals. During normal operation, the Lane module is always in the control mode or high-speed mode. High-speed operations happen in bursts and start from and end in the Stop state (LP-11).
Important: When
designing a system, a low-power line state of less than 20 ns transmitted by this core can
be ignored by the corresponding AMD MIPI RX PHY core.
The following sections describe the features in detail for the MIPI TX C-PHY/D-PHY core.