The MIPI TX C-PHY/D-PHY IP is a physical layer that supports the MIPI CSI-2 and DSI protocols. It is a combo PHY that can be configured as either a C-PHY or a D-PHY. The core consists of an analog front end to generate and receive the electrical level signals, and a digital back end to control the I/O functions. A typical TX configuration consists of one clock lane and one to four data lanes in D-PHY mode. The C-PHY/D-PHY link supports a high-speed (HS) mode for fast data traffic and a low-power (LP) mode for control transactions.
- In HS mode, the low-swing differential signal supports data transfers from 400 to 4500 Mb/s for D-PHY and 400 to 4500 Msps for C-PHY.
- In LP mode, all wires operate as a single-ended line capable of supporting 10 Mb/s asynchronous data communications.