PROGRAMMABLE SEQUENCE CONTROL Register (0x38) - PROGRAMMABLE SEQUENCE CONTROL Register (0x38) - 1.0 English - PG436

MIPI TX C-PHY/D-PHY LogiCORE IP Product Guide (PG436)
Document ID
PG436
Release Date
2025-11-20
Version
1.0 English

The Programmable Sequence register is used to enable programmable sequence for HS Packets. The following table provides the register bit description. This register is used in C-PHY configuration only.

Table 1. Programmable Sequence Control Register Bit Description
Bits Name Default Value Access type Description
[31:1] Reserved 0x0 RO Reserved
[0] prog_seq_ctrl 0x0 R/W Enable Programmable Sequence for HS Packets Writing '1' Enables the C-PHY Controller to transmit Programmable Sequence