PPI Signals - PPI Signals - 1.0 English - PG436

High-Speed Transmit Data.

High-Speed data to be transmitted. The signal connected to TxDataHS[0] is associated with bit 0 of the C-PHY Mapping function. If a 32-bit transmit data path is used then TxDataHS[16] is also associated with bit 0 of the C-PHY Mapping function, and if TxWordValidHS[1:0] = 11, then the seven symbols associated with TxDataHS[31:16] are transmitted after the seven symbols associated with TxDataHS[15:0]. Data is captured on rising edges of TxWordClkHS. The following signals are defined for the High-Speed Transmit Data based on the width of the transmit data path:

• 16-bit width – TxDataHS[15:0]
• 32-bit width – TxDataHS[31:0]

High-Speed Transmit Ready.

High-Speed Transmit Request and Data Valid.

High-Speed Command to Transmit Sync Word

The protocol adapter attached to the C-PHY might need to transmit Sync Words to separate multiple copies of a packet header. This command signal has the same timing as High-Speed Transmit Data on the PPI, but when a TxSendSyncHS signal is active on a given TxWordClkHS cycle then the corresponding 16 bits of High-Speed Transmit Data is ignored and the C-PHY transmits a Sync Word in place of the corresponding High-Speed Data Word for any Word Clock cycle where a TxSendSyncHS signal is active. The following Transmit Sync Word signals are defined based on the width of the transmit data path:

• 16-bit width – TxSendSyncHS[0]
• 32-bit width – TxSendSyncHS[1:0]

The following Transmit Sync Word signals cause a Sync Word to be transmitted as follows:

• TxSendSyncHS[0] – transmit a Sync Word inplace of the C-PHY mapped version ofTxDataHS[15:0]
• TxSendSyncHS[1] – transmit a Sync Word inplace of the C-PHY mapped version ofTxDataHS[31:16]

High-Speed Transmit Word Data Valid

When the High-Speed Transmit Data width is greater than 16 bits it is necessary to indicate which 16-bit segments contain valid transmit data to be able to transmit any number of words. The following Transmit Word Data Valid signals are defined based on the width of the CPHY datapath:

• 16-bit width – TxWordValidHS[0]
• 32-bit width – TxWordValidHS[1:0]

The following Transmit Word Data Valid signals indicate which bits of the TxDataHS data bus contain valid data to transmit as follows:

• TxWordValidHS[0] –TxDataHS[15:0] containsvalid data to be transmitted
• TxWordValidHS[1] – TxDataHS[31:16] contains valid data to be transmitted For a 16-bit transmit data width, TxWordValidHS[0] is driven to 1’b1 when txrequesths is asserted. For a 32-bit transmit data width with multiple words being transferred, TxWordValidHS[1:0] is driven to 0x3 on the first word of the data transfer and either 0x1 or 0x3 on the last word of the data transfer. If there are more than 2 words transferred, TxWordValidHS[1:0] is driven to 0x3 for all of the middle word data transfers. If only one word is being transferred, TxWordValidHS[1:0] is driven to either 0x1 or 0x3.

The following Transmit Word Data Valid signals are defined based on the width of the D-PHY transmit data path:

• 8-bit width – TxWordValidHS[0]
• 16-bit width – TxWordValidHS[1]

• TxWordValidHS[0] –TxDataHS[7:0] contains valid data to be transmitted
• TxWordValidHS[1] – TxDataHS[15:8] contains valid data to be transmitted for a 16- bit transmit data width,

TxWordValidHS[0] is driven to 1’b1 when txrequesths is asserted. For a 16-bit transmit data width with multiple words being transferred.

TxWordValidHS[1:0] is driven to 0x3 on the first word of the data transfer and either 0x1 or 0x3 on the last word of the data transfer.

If there are more than 2 words transferred, TxWordValidHS[1:0] is driven to 0x3 for all of the middle word data transfers. If only one word is being transferred, TxWordValidHS[1:0] is driven to either 0x1 or 0x3.

dl_txtransf erenhs

High-Speed TX Data Transfer Enable

This active-High signal that

is synchronous to TXWordClkHS

indicates to the PHY that TXDataHS

is valid. The PHY must continue

to transmit the Preamble even

if TXReadyHS is asserted until

TXDataTransferEnHS is asserted.

Once asserted, the protocol layer

can only deassert this signal when

TXRequestHS is also deasserted.

TXDataTransferEnHS can be tied to

‘1’, if the protocol layer does not

support High Speed TX Data Transfer

Enable or if it does not want to

throttle TXDataHS at the beginning

of a HS data transfer.

Both C-PHY

and D-PHY

High-Speed Transmit Data Width Select

Selects the bus width of TxDataHS:

• TxDataWidthHS[1:0] = 00: not used, reserved.
• TxDataWidthHS[1:0] = 01: 16-bit, TxDataHS[15:0]
• TxDataWidthHS[1:0] = 10: 32-bit, TxDataHS[31:0]
• TxDataWidthHS[1:0] = 11: not used, reserved.

High-Speed Command to choose the Sync Type

When TxSendSyncHS[0] is asserted then TxSyncTypeHS0[2:0] selects which type of Sync Word is transmitted. Similarly, When TxSendSyncHS[1] is asserted then TxSyncTypeHS1[2:0] selects which type of Sync Word is transmitted. The mapping of Sync Type to the actual Sync Word value is specified in Section 6.4.4.2. The default Sync Word, 3444443, is Sync Type 3 and is selected using the binary value 011.

The following Sync Type Command signals are defined based on the width of the receive data path:

• 16-bit width – TxSyncTypeHS0[2:0]
• 32-bit width – TxSyncTypeHS0[2:0] andTxSyncTypeHS1[2:0]

High-Speed Command to choose the Sync Type

When TxSendSyncHS[0] is asserted then TxSyncTypeHS0[2:0] selects which type of Sync Word is transmitted. Similarly, When TxSendSyncHS[1] is asserted then TxSyncTypeHS1[2:0] selects which type of Sync Word is transmitted. The mapping of Sync Type to the actual Sync Word value is specified in Section 6.4.4.2. The default Sync Word, 3444443, is Sync Type 3 and is selected using the binary value 011.

The following Sync Type Command signals are defined based on the width of the receive data path:

• 16-bit width – TxSyncTypeHS0[2:0]
• 32-bit width – TxSyncTypeHS0[2:0] andTxSyncTypeHS1[2:0]

This optional control bus selects which type of Preamble is transmitted. It can be a normal Preamble or a Format 1, Format 2, or Format 3 Calibration Preamble. Selects which type of Preamble is transmitted:

• TxPreambleTypeHS[1:0] = 00: normal Preamble.
• TxPreambleTypeHS[1:0] = 01: Format1 Calibration Preamble
• TxPreambleTypeHS[1:0] = 10: Format2 Calibration Preamble
• TxPreambleTypeHS[1:0] = 11: Format3 Calibration Preamble

High-Speed Transmit Skew Calibration.

This is an optional pin to initiate the periodic deskew burst at the transmitter.A low-to-high transition on TxSkewCalHS causes the PHY to initiate a deskew calibration.A high-to-low transition on TxSkewCalHS causes the PHY to stop deskew pattern transmission and initiate an end-oftransmission sequence.

High-Speed Transmit Alternate Calibration.

This is an optional signal to initiate the alternate calibration sequence at the transmitter. A low-to-high transition on TxAlternateCalHS causes the PHY to initiate an alternate calibration sequence. A high-to-low transition on TxAlternateCalHS causes the PHY to stop the alternate calibration sequence and initiate an end-of transmission sequence. The assertion of this signal is mutually exclusive with the assertion of the txrequesths, TxSkewCalHS, and TxRequestEsc signals.

When TxAlternateCalHS is asserted, txrequesths will be asserted on the clock Lane. All data Lanes for a Link can initiate alternate calibration sequence at the same time. It is up to the protocol layer to ensure TxAlternateCalHS is only asserted after the initial deskew pattern and before any High Speed data transfers.

High-Speed Transmit Word Clock

This is used to synchronize PPI signals in the High Speed transmit clock domain. AMD recommends that all transmitting Lane Modules share one TxWordClkHS signal. The frequency of TxWordClkHS is dependent upon the width of the High-Speed Transmit Data, as follows:

• 16-bit width, TxDataHS[15:0], the High-Speed Transmit Word Clock is exactly 1/7 the HighSpeed symbol rate.
• 32-bit width, TxDataHS[31:0], the High-Speed Transmit Word Clock is exactly 1/14 the HighSpeed symbol rate.

Force Lane to Generate Stop State.

This signal allows the protocol to force a lane module into the Stop state during initialization or following an error situation, such as an expired timeout. When this signal is High, the lane module state machine is immediately forced into the Stop state.

Lane is in Stop state.

This active-High signal indicates that the Lane module (TX or RX) is currently in the Stop state. Also, the protocol can use this signal to indirectly determine if the PHY line levels are in the LP-11 state.

Enable Lane Module.

This active-High signal forces the lane module out of “shutdown.” All line drivers, receivers, terminators, and contention detectors are turned off when Enable is Low. When Enable is Low, all other PPI inputs are ignored and all PPI outputs are driven to the default inactive state. Enable is level sensitive and does not depend on any clock.

ULP State (not) Active.

This active-Low signal is asserted to indicate that the Lane is in the ULP state. For a receiver, this signal indicates that the Lane is in the Ultra Low Power (ULP) state. At the beginning of the ULP state, ulpsactivenot is asserted together with rxulpsesc, or rxclkulpsnot for a clock lane. At the end of the ULP state, this signal becomes inactive to indicate that the Mark-1 state has been observed. Later, after a period of time (Twakeup), the rxulpsesc (or rxclkulpsnot) signal is deasserted.

Transmit Ultra-Low Power State on Clock Lane.

This active-High signal is asserted to cause a clock lane module to enter the ULP state. The lane module remains in this mode until txulpsclk is deasserted.

Transmit ULP Exit Sequence.

This active-High signal is asserted when the ULP state is active and the protocol is ready to leave the ULP state. The PHY leaves the ULP state and begins driving Mark-1 after txulpsexit is asserted. The PHY later drives the Stop state (LP-11) when txrequestesc is deasserted.

txulpsexit is synchronous to txclkesc. This signal is ignored when the lane is not in the ULP state.

ULP State (not) Active.

This active-Low signal is asserted to indicate that the Lane is in the ULP state. For a receiver, this signal indicates that the Lane is in the Ultra Low Power (ULP) state. At the beginning of the ULP state, ulpsactivenot is asserted together with rxulpsesc, or rxclkulpsnot for a clock lane. At the end of the ULP state, this signal becomes inactive to indicate that the Mark-1 state has been observed. Later, after a period of time (Twakeup), the rxulpsesc (or rxclkulpsnot) signal is deasserted.

High-Speed Transmit Request and Data Valid.

For clock lanes, this active-High signal causes the lane module to begin transmitting a high-speed clock.

Lane is in Stop state.

This active-High signal indicates that the Lane module (TX or RX) is currently in the Stop state. Also, the protocol can use this signal to indirectly determine if the PHY line levels are in the LP-11 state.

Enable Lane Module.

This active-High signal forces the lane module out of “shutdown.” All line drivers, receivers, terminators, and contention detectors are turned off when Enable is Low. When Enable is Low, all other PPI inputs are ignored, and all PPI outputs are driven to the default inactive state. Enable is level sensitive and does not depend on any clock.

Escape Mode Transmit Clock.

This clock is directly used to generate escape sequences.

Escape Mode Transmit Request.

This active-High signal, asserted together with exactly one of txlpdtesc, txulpsesc, or one bit of txtriggeresc, is used to request entry into escape mode. When in escape mode, the lane stays in escape mode until txrequestesc is deasserted.

txrequestesc is only asserted by the protocol while txrequesths is Low.

txrequesths has highest priority than txrequestesc.

Escape Mode Transmit Ultra-Low Power State.

This active-High signal is asserted with txrequestesc to cause the lane module to enter the ultra-low power state. The lane module remains in this mode until txrequestesc is deasserted.

txlpdtesc and all bits of txtriggeresc[3:0] are Low when txulpsesc is asserted.

Transmit ULP Exit Sequence.

This active-High signal is asserted when the ULP state is active and the protocol is ready to leave the ULP state. The PHY leaves the ULP state and begins driving Mark-1 after txulpsexit is asserted. The PHY later drives the Stop state (LP-11) when txrequestesc is deasserted. txulpsexit is synchronous to txclkesc. This signal is ignored when the lane is not in the ULP state.

Escape Mode Transmit Trigger 0-3.

One of these active-High signals is asserted with txrequestesc to cause the associated trigger to be sent across the lane interconnect. In the receiving lane module, the same bit of rxtriggeresc is then asserted and remains asserted until the lane interconnect returns to the Stop state, which happens when txrequestesc is deasserted at the transmitter. Only one bit of txtriggeresc[3:0] is asserted at any given time, and only when txlpdtesc and txulpsesc are both Low. The following mapping is done by the D-PHY TX module:

• Reset-Trigger→txtriggeresc[3:0] = 4’b0001
• Unknown-3→txtriggeresc[3:0] = 4’b0010
• Unknown-4→txtriggeresc[3:0] = 4’b0100
• Unknown-5→txtriggeresc[3:0] = 4’b1000

Escape Mode Transmit Low-Power Data.

This active-High signal is asserted with txrequestesc to cause the lane module to enter low-power data transmission mode. The Lane module remains in this mode until txrequestesc is deasserted.

txulpsesc and all bits of txtriggeresc[3:0] are Low when txlpdtesc is asserted.

Escape Mode Transmit Data.

This is the eight-bit Escape mode data to be transmitted in lowpower data transmission mode. The signal connected to txdataesc[0] is transmitted first. Data is captured on rising edges of txclkesc.

Escape Mode Transmit Data Valid.

This active-High signal indicates that the protocol is driving valid data on txdataesc[7:0] to be transmitted. The lane module accepts the data when txrequestesc, txvalidesc, and txreadyesc are all active on the same rising txclkesc clock edge.

Escape Mode Transmit Ready. This active-High signal indicates that txdataesc[7:0] is accepted by the lane module to be serially transmitted.

txreadyesc is valid on rising edges of txclkesc.