The following figure shows the MIPI TX C-PHY/D-PHY core architecture for AMD Versal™ and AMD Versal™ Gen 2 Adaptive SoC devices. The MIPI TX C-PHY/D-PHY core has three major blocks:
- C-PHY or D-PHY Controller
- Either C-PHY or D-PHY controller is implemented based on the selection. The input is PPI, common for both C-PHY and D-PHY, but the output signals are different. C-PHY output has three signals called trio A, B, and C. D-PHY output has one clock lane and four data lanes.
- XPHY Logic
- This block performs serialization and has clocking implementation for the PHY.
- Register Interface
- Optional AXI4-Lite register interface to control mandatory protocol timers and registers.
Figure 1. MIPI TX C-PHY Core Architecture
Figure 2. MIPI TX D-PHY Core Architecture
