In MIPI D-PHY, clock and data lanes are implemented in pin pairs, which are illustrated above as pins that share an X5PHIO_XCVR_X2 site and have a pin name that indicate that they are P and N pairs. For example IO_L0P_H0O0P1_700 and IO_L0N_H0O0N1_700 are a pair because they share the same bank an the IO_L0P and IO_L0N portion of the pin name are paired. It is important that D-PHY pins maintain the "P" and "N" in the IP name as the pin site. Swapping these pins is not allowed.
Due to shared clocking resources, interfaces within the same bank must share the same line rate. When combining multiple interfaces into the same bank, only one core must be generated to "include shared logic" to allow its X5PLL interface to be shared.