MIPI C-PHY TX Guidelines - MIPI C-PHY TX Guidelines - 1.0 English - PG436

In MIPI C-PHY, clock and data lanes are implemented in pin triplets, which are illustrated above as pins that share an Triplet Interface Group, and have fixed Line A, B, C positions. Swapping these pins is not allowed. When a C-PHY Triplet is used, PIn P3 for Interface Group A and Pin P5 for interface can only be used as TX and must bypass the PHY resources (that is, must be driven from the fabric, not the PHY).

Due to shared clocking resources, interfaces within the same bank must share the same line rate. When combining multiple interfaces into the same bank, only one core must be generated to "include shared logic" to allow its X5PLL interface to be shared.